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An often heard criticism about Intel (NASDAQ:INTC ) is that even if the company executes on its leadership process technology roadmap, it supposedly doesn’t have EUV lithography machines from ASML (ASML) to ramp these nodes in volume. This would obviously prevent Intel from capitalizing on its opportunity.

However, I believe this is most likely misinformation. While it is true demand is outpacing supply for EUV tools, there is nevertheless a steady and growing supply. This means Intel should be able to secure enough tools as it ramps into volume production. In fact, a calculation suggests Intel may already have (more than) twice as many EUV tools as it will need in the first year of ramp.

This article is in part a follow-up to my recent analysis of TSMC’s (TSM) N2 delay. I saw a comment that asked why I didn’t reply to comments. The blunt answer is that most reactions simply stated that TSMC was the unquestioned leader as if it were a fact (that could never change). However, the whole point of that article was to challenge what people thought they knew was true about TSMC.

For comparison, if one would go back exactly 1 decade, one could make exactly the same claims about Intel and its leadership position, like people are now still largely believing about TSMC. At that time, TSMC was having major issues at 20nm while Intel was steamrolling ahead with FinFET. The times have changed and will (could) do so again in the future. To be specific, TSMC reorganized its development while Intel then ran into its own issues at 10nm.

As further case in point, some people thought the article was based on rumors, while the quotes I provided literally came from TSMC’s CEO.

Nevertheless, one tangible argument I saw was that Intel supposedly doesn’t have enough EUV tools to ramps its process technologies into production. So even if Intel executes flawlessly on its roadmap, it still wouldn’t be able to ship these nodes. More specifically, I was referred to this article that spoke about a “scarcity of EUV tools”. I think this is overblown, so I want to substantially nuance that claim.

First, we know TSMC has ramped 5nm into high volume production since Q2 2020 for its highest revenue customer, Apple (AAPL), despite that at that point in time ASML had shipped a cumulative amount of HVM EUV tools of “just” 44 in the previous two years. For comparison, ASML shipped 42 EUV tools in 2021 alone. So not only has ASML already doubled its EUV tool manufacturing capacity, but the relatively few amount of tools that ASML had shipped by 2021 allowed TSMC to successfully ramp production for its most demanding customer anyway.

Moreover, what this also means is that one might expect that, given that TSMC (and to a lesser extent Samsung) has already been scavenging EUV tools for several years, its demand for more EUV tools should hence be somewhat reduced. Although one could argue that TSMC will soon be ramping 3nm, in the case of Apple, this simply means that Apple will be buying less 5nm wafers and more 3nm wafers.

Furthermore, the table below shows that ASML is continuing to ramp its capacity for EUV tools. ASML targets 55 shipments in 2022 and at its recent Q1 earnings call announced a plan to target (up to) 90 tools by 2025. In fact, ASML was asked many questions about this guidance during the earnings call, and ASML admitted that 90 would actually likely be more than the actual demand it will have in 2025: ASML described this as its plan to cater to the forecasted $1 trillion semiconductor industry by 2030.

In other words, while it is the case that EUV supply is somewhat tight, ASML is investing aggressively to go from being behind to being ahead of the demand curve.

Hence, supply should exceed demand by 2025, so any issues will likely be solved within the next three years.

More in general, just like the overall semiconductor shortages, the reason that there is a shortage is because demand continues to exceed the already high amount of supply. The supply itself is not low. This in turn means that Intel very likely should still be able to manufacture a large amount of EUV wafers in the next few years.

Yet another argument is that people seem to assume that Intel is for some reason last in the line to secure EUV capacity. The table above is a very sad illustration of this. However, in reality there is simply no evidence for this assumption that TSMC is gobbling up all of ASML’s capacity.

While this may actually have been true in the past, this was simply because Intel had no demand for EUV tools yet, while as discussed above, it is unrealistic that TSMC’s demand for EUV will just continue to increase indefinitely despite that it has already been able to ramp its largest customer two years ago.

Simply put, assuming a roughly even split, Intel should be able to secure on the order of 15 tools this year alone. This should make sense given that TSMC and Intel have (to first approximation) the same wafer capacity at the leading edge, so both will need a roughly equal amount of tools eventually.

As case in point, YouTube channel TechTechPotato visited Intel's Oregon fab a while ago and was able to spot numerous tools. Although the total wasn't disclosed, a commenter claimed he saw 15 of the C tool (ASML started shipping the D tool since 2021).

This all begs the question, how much capacity does this amount of tools provide? We know that Intel will use on the order of 15 EUV layers, which means that it needs 15 tools per 45k wafer starts per month.

With 15 tools, Intel will be able to fill one 45k wafer starts per month fab. I have done the math, assuming conservative yield numbers, and with this amount of tools, Intel should be able to manufacture over 200 million Meteor Lake CPUs per year. In fact, in reality it should likely be even more than this, since it is well known by now that Intel will be using chiplets for Meteor Lake. This means that only the relatively small CPU tile is built on Intel 4. The GPU tile is manufactured at TSMC, presumably on 3nm.

So not only does this provide another argument for why Intel will not be short of EUV capacity (since every tool that goes to TSMC could in principle be used to supply Intel chiplets anyway), but given that only half to a third of the silicon area will be Intel 4, this means in reality Intel may have a theoretical capacity for 400 or even 600 million Meteor Lake CPUs with just 15 tools. This is more than there are PCs sold in total.

For comparison, Intel announced in January, well over a year after its launch, that it had shipped 100 million Tiger Lake CPUs. Note that Intel has called Tiger Lake its fastest shipping notebook CPU in history. So if using a conservative amount of EUV tools already yields a number that is twice as much as Intel’s fastest ramping CPU ever, then can we really speak about a EUV shortage?

Of course, Intel will also have to ramp desktop CPUs, but notebooks represent about two-thirds of the CPU market. Intel will also have to ramp its data center CPUs, but Intel announced that it won’t ramp its EUV nodes (starting with Intel 3) into the data center until 2024. While Intel 3 will use a few more EUV layers, the ramp will also start a year later, allowing Intel to secure even more tools in the meantime.

In summary, EUV first went in volume production for one of the world’s most demanding customers, Apple, already two years ago. Since then, not only has TSMC continued to gobble up the majority of ASML's EUV production (since Intel is late to EUV), ASML has only further increased its EUV output, on track to double its 2019 capacity this year. There is no evidence Intel is somehow being put last in line to receive tools, and even using a conservative estimate of Intel securing only 15 tools yields an estimate that allows Intel to double the ramp of Tiger Lake, which was already its fastest ramping CPU ever.

But this is not all. There is one more argument. A while ago someone tweeted to me (something along the lines of) that I seemed to assume that Intel would somehow be able to manufacture 4x (or however much it was) more chips than TSMC with the same tools. To which I replied: yes.

The subtle point is that the assumption that Intel will be using the same EUV tools as TSMC is flawed. When TSMC started EUV production in 2020 for Apple, this was mainly based on the NXE:3400B tool, which is rated at 125WPH (wafers per hour). Since, then, ASML has shipped the NXE:3400C and since 2021 the NXE:3600D. The roadmap then goes to the NXE:3800E in mid-2023 and the NXE:4000F in 2025.

The D tool that Intel will primarily be buying for its initial EUV ramp has a capacity of 160WPH, which is almost 30% higher than the B tool. The E tool that Intel will buy for its upcoming fabs in Israel, Arizona and Ohio will have a throughput of up to 220WPH.

This means that in total ASML will actually ship about 2.7x more EUV throughput capacity in 2022 than in 2019. If ASML succeeds in its plan to ship 90 E tools in 2025, then it will have shipped nearly 5x more wafer throughput capacity than in 2020. Note, though, that admittedly some of that throughput will be used to increase the EUV layer count per wafer, but the overall point remains. For example, in my calculation above where I used 15 EUV tools, in reality, Intel may actually only need about 12 of the D/E tools.

While concerns about Intel’s EUV capacity was a major point, the other main argument I saw was a lack of confidence from investors in Intel’s ability to execute on its process roadmap. However, as indicated above, I have not seen tangible evidence to back this up aside from people relying on the past to extrapolate to the future.

I would remind that this is exactly the Intel investment thesis: while the stock market continues to value Intel based on the past, the current information already provides a lot more clarity about where Intel will be in the future.

To wit, Intel has said that all of its nodes through 18A are either on track or ahead of schedule. In fact, at Investor Meeting, Intel had shown an 18A test wafer and also pulled in 18A from Q1 2025 to H2’24 as a strong sign of confidence in its execution.

But there is more. This is what Intel’s SVP of Technology Development said at Investor Meeting:

Working in conjunction with a foundry customer, we recently delivered an 18A wafer that exceeded our customer’s expectations. We expect to have two [foundry] test chips on 18A taped out during 2022 and four by H1’23.

One criticism was that the wafer Pat Gelsinger showed was “just” an SRAM wafer, which is the easiest kind of structure to manufacture as test vehicle during development. However, the statement above clearly goes a step further, indicating that Intel is already busy with real test chips… for its foundry customers. So either this suggests that Intel’s early foundry customers are just as far along in development as Intel, or if Intel is ahead of its foundry customers then Intel may already be running its own test chips in its development production lines as well.

Either way, the investor takeaway here is that while 20A and 18A are still quite a while out, in reality this technology is already tangible even today. Intel has been developing this stuff for years now, and is now in the what should be seen as the final stretches in development to bring this to market. In other words, barring some unexpected issues late in development (as was admittedly the case for Intel 4), Intel’s confidence is warranted.

This section describes a bull scenario (although currently one without any evidence for) under which I would overnight quadruple my Intel stake.

One quite tantalizing possibility (at least for Intel shareholders) that I have discussed in my recent TSMC 2nm article was whether the 18A pull-in would allow Intel to also pull-in the next-gen 14A node to H2 2025. This would be the opposite of a delay, which usually sets back the whole roadmap: now the whole roadmap would be pulled in by two quarters.

If that were the case, then this would mean that Intel would have fully "undelayed" its process roadmap since the 7nm delay in mid-2020. Indeed, two times a 6 month pull-in would undo the 12 month delay from 2020. In other words, Intel would be completely back on track to its original 2019-2029 roadmap.

Essentially, this would also imply that Intel would be doing two "accelerated" process node transitions (18 months per node instead of 24 months) back-to-back, twice as fast as TSMC's 2nm cadence. Although it isn't sure when Intel will even announce its roadmap beyond 18A, if this bull case materializes I would overnight quadruple my Intel stake: Intel would already be going to its third-gen RibbonFET while TSMC would be ramping its first-gen.

Investors may wonder if it is feasible or even realistic to expect such a scenario: most people didn't think Intel could accelerate even 1 node (20A), so never mind two nodes. Although I deem the chance to be slim, it is certainly not impossible.

The reason for this is because Intel has already showed research at engineering conferences (in 2020 and 2021) where it was able to stack two RibbonFET transistors in 3D. This by itself could (nearly) double transistor density without having to shrink the transistor itself. Hence, this should actually be a quite straightforward node to execute on. The technical name for this is CFET or complementary FET, since the PMOS and NMOS (together CMOS) are stacked.

Intel: [T]his first-of-a-kind self-aligned 3-D stacked CMOS with multi-nanoribbons Si show higher on-state current at lower supply voltage than other demonstration in literature.

Given that this would also be Intel's second-gen high-NA EUV process, the risks for this generation seem very low.

What I like about being an Intel bull right now is that people do not take Intel’s claims for granted, but instead they demand evidence in terms of products they can buy in the market. However, for those who are just willing to look, there is actually already a lot of evidence for Intel’s progress. This may allow investors to get ahead of where the stock might eventually go to.

First, people said Intel tried to become a foundry before and failed. However, Pat Gelsinger created Intel Foundry Services with a dedicated P&L and with a dedicated and experienced foundry leader. This has not only resulted in terrific customer feedback (“the best foundry engagement experienced they’ve had”, according to Intel), but will also result in two 18A test chips in 2022 and two more in first half of 2023, undoubtedly followed by real tape outs in 2023 and 2024. This also provides a tangible proof point for the second criticism, that Intel’s process roadmap is just a roadmap.

Thirdly, given how much evidence there is by now for Intel’s vastly improved process execution, the last bastion for the bears has now become to say that Intel supposedly won’t be secure enough EUV tool capacity. Indeed, if we have to believe the analyst pundits, Intel only got 2/42 EUV tools last year and will only get 3/55 this year. Intel is last in line, as it has supposedly been put there by Peter Wennink himself.

However, as I have pointed out there is already video/anecdotal evidence that Intel has much more than two tools. If anything, the simple reason why this can’t be the case is because even the biggest Intel bears have said that Pat Gelsinger comes across as a salesman. He has even visited Taiwan twice in the last few quarters to meet TSMC management personally, for example. So if anyone would be able to let Intel get first in line for EUV tools, it would be Gelsinger. As mentioned, all the while ASML is aggressively expanding production and introducing new tools with higher throughput.

In any case, a rough calculation (based on official ASML guidance and using conservative assumptions) has indicated that Intel should be able to manufacture about as many Meteor Lake CPUs as there are PCs sold in total (per year) with just a dozen or so EUV tools. This is especially the case given that only the relatively small CPU chiplet will be manufactured on Intel 4, with the rest being produced on other nodes, including the GPU at TSMC. In other words, Intel's decision to introduce chiplets (for completely unrelated reasons) in now paying big dividends to circumvent any supposed EUV shortage.

Overall, given Intel’s execution in the last two years, which as I have discussed previously is in stark contrast to TSMC’s execution in the last two years, there do not seem to be any roadblocks that will prevent Intel from regaining technology leadership.

Pat Gelsinger ’s brilliant plan to start a serious foundry business, for which he has assembled a world-class team, will allow Intel to capitalize on these changing dynamics to the fullest possible extent. Each leading edge chip that will be taped out over the next few years at Intel will be one that was taken from either Samsung or TSMC.

This article was written by

Disclosure: I/we have a beneficial long position in the shares of INTC either through stock ownership, options, or other derivatives. I wrote this article myself, and it expresses my own opinions. I am not receiving compensation for it (other than from Seeking Alpha). I have no business relationship with any company whose stock is mentioned in this article.